root/trunk/jps2ps/package/logic.pps

/uselogic {} def
/logicUnit .5 def
/logicNInput 2 def
/logicWireLength .5 def

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

/AND_dic 15 dict def
/AND_dim {
   logicWireLength neg 0 jtoppoint
   4.5 logicUnit mul logicWireLength add 4 logicUnit mul jtoppoint
} def
/AND {
gsave
8 dict begin
   currentpoint translate
   /h_and 4 logicUnit mul def
   /inter h_and logicNInput div def
   0   0 logicUnit mulv /z1 defpoint
   0   4 logicUnit mulv /z2 defpoint
   2.5 4 logicUnit mulv /z3 defpoint
   4.5 2 logicUnit mulv /z4 defpoint
   2.5 0 logicUnit mulv /z5 defpoint
   [z1 -- z2 -- z3 {right} .. {down} z4 .. {left} z5 -- z1] draw
   [z4 z4 logicWireLength 0 addv] ligne
   /i 0 def
   logicNInput {
      AND_dic (in) i chaine cvs append cvlit
         [ logicWireLength neg inter i .5 add mul ] cvx put
      /i i 1 add store
   } repeat
   AND_dic /out {4.5 2 logicUnit mulv logicWireLength 0 addv} bind put
   /i 0 def
   logicNInput {
      [ 0 inter i .5 add mul dupp logicWireLength neg 0 addv] ligne
      /i i 1 add store
   } repeat
   /logicNInput 2 store
end
grestore
} def

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

/NAND_dic 15 dict def
/NAND_dim {
   logicWireLength neg 0 jtoppoint
   5.1 logicUnit mul logicWireLength add 4 logicUnit mul jtoppoint
} def
/NAND {
gsave
8 dict begin
   currentpoint translate
   /h_nand 4 logicUnit mul def
   /inter h_nand logicNInput div def
   0   0 logicUnit mulv /z1 defpoint
   0   4 logicUnit mulv /z2 defpoint
   2.5 4 logicUnit mulv /z3 defpoint
   4.5 2 logicUnit mulv /z4 defpoint
   2.5 0 logicUnit mulv /z5 defpoint
   [z1 -- z2 -- z3 {right} .. {down} z4 .. {left} z5 -- z1] draw
   z4 .3 logicUnit mul 0 addv .3 logicUnit mul cercle
   [z4 .6 logicUnit mul 0 addv dupp logicWireLength 0 addv] ligne
   /i 0 def
   NAND_dic /out {5.1 2 logicUnit mulv logicWireLength 0 addv} bind put
   logicNInput {
      NAND_dic (in) i chaine cvs append cvlit
         [ logicWireLength neg inter i .5 add mul ] cvx put
      /i i 1 add store
   } repeat
   /i 0 def
   logicNInput {
      [ 0 inter i .5 add mul dupp logicWireLength neg 0 addv] ligne
      /i i 1 add store
   } repeat
   /logicNInput 2 store
end
grestore
} def

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

/OR_dic 15 dict def
/OR_dim {
   logicWireLength neg 0 jtoppoint
   4.5 logicUnit mul logicWireLength add 4 logicUnit mul jtoppoint
} def
/OR {
gsave
8 dict begin
   currentpoint translate
   /h_or 4 logicUnit mul def
   /inter h_or logicNInput div def
   0   0 logicUnit mulv /z1 defpoint
   0   4 logicUnit mulv /z2 defpoint
   1.5 4 logicUnit mulv /z3 defpoint
   4.5 2 logicUnit mulv /z4 defpoint
   1.5 0 logicUnit mulv /z5 defpoint
   .75 2 logicUnit mulv /z6 defpoint
   [z4 dupp logicWireLength 0 addv] ligne
   /i 0 def
   OR_dic /out {4.5 2 logicUnit mulv logicWireLength 0 addv} bind put
   logicNInput {
      OR_dic (in) i chaine cvs append cvlit
         [ logicWireLength neg inter i .5 add mul ] cvx put
      /i i 1 add store
   } repeat
   /i 0 def
   logicNInput {
      [logicUnit inter i .5 add mul dupp logicWireLength neg logicUnit sub 0 addv] ligne
      /i i 1 add store
   } repeat
   gsave
   newpath
      z1 smoveto
      [z1 .. z6 .. z2] draw_
      [z2 z3] ligne_
      [z3 {right} .. {1 -2} z4] draw_
      [z4 {-1 -2} .. {left} z5] draw_
      [z5 z1] ligne_
      blanc fill
   grestore
   [z1 .. z6 .. z2] draw
   [z2 z3] ligne
   [z3 {right} .. {1 -2} z4] draw
   [z4 {-1 -2} .. {left} z5] draw
   [z5 z1] ligne
   /logicNInput 2 store
end
grestore
} def

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

/NOR_dic 15 dict def
/NOR_dim {
   logicWireLength neg 0 jtoppoint
   5.1 logicUnit mul logicWireLength add 4 logicUnit mul jtoppoint
} def
/NOR {
gsave
8 dict begin
   currentpoint translate
   /h_nor 4 logicUnit mul def
   /inter h_nor logicNInput div def
   0   0 logicUnit mulv /z1 defpoint
   0   4 logicUnit mulv /z2 defpoint
   1.5 4 logicUnit mulv /z3 defpoint
   4.5 2 logicUnit mulv /z4 defpoint
   1.5 0 logicUnit mulv /z5 defpoint
   .75 2 logicUnit mulv /z6 defpoint
   z4 .3 logicUnit mul 0 addv .3 logicUnit mul cercle
   [z4 .6 logicUnit mul 0 addv dupp logicWireLength 0 addv] ligne
   /i 0 def
   NOR_dic /out {5.1 2 logicUnit mulv logicWireLength 0 addv} bind put
   logicNInput {
      NOR_dic (in) i chaine cvs append cvlit
         [ logicWireLength neg inter i .5 add mul ] cvx put
      /i i 1 add store
   } repeat
   /i 0 def
   logicNInput {
      [logicUnit inter i .5 add mul dupp logicWireLength neg logicUnit sub 0 addv] ligne
      /i i 1 add store
   } repeat
   gsave
   newpath
      z1 smoveto
      [z1 .. z6 .. z2] draw_
      [z2 z3] ligne_
      [z3 {right} .. {1 -2} z4] draw_
      [z4 {-1 -2} .. {left} z5] draw_
      [z5 z1] ligne_
      blanc fill
   grestore
   [z1 .. z6 .. z2] draw
   [z2 z3] ligne
   [z3 {right} .. {1 -2} z4] draw
   [z4 {-1 -2} .. {left} z5] draw
   [z5 z1] ligne
   /logicNInput 2 store
end
grestore
} def

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

/XOR_dic 15 dict def
/XOR_dim {
   logicWireLength neg 0 jtoppoint
   5.25 logicUnit mul logicWireLength add 4 logicUnit mul jtoppoint
} def
/XOR {
gsave
8 dict begin
   currentpoint translate
   /h_xor 4 logicUnit mul def
   /inter h_xor logicNInput div def
   .75  0 logicUnit mulv /z1 defpoint
   .75  4 logicUnit mulv /z2 defpoint
   2.25 4 logicUnit mulv /z3 defpoint
   5.25 2 logicUnit mulv /z4 defpoint
   2.25 0 logicUnit mulv /z5 defpoint
   1.5  2 logicUnit mulv /z6 defpoint
   0    0 logicUnit mulv /z7 defpoint
   0    4 logicUnit mulv /z8 defpoint
   .75  2 logicUnit mulv /z9 defpoint
%   1.5 3 add .75 add 1 2 div add 2 logicUnit mulv /z10 defpoint
%   z4 .3 logicUnit mul 0 addv .3 logicUnit mul cercle
   [z4 dupp logicWireLength 0 addv] ligne
   /i 0 def
   XOR_dic /out {5.25 2 logicUnit mulv logicWireLength 0 addv} bind put
   logicNInput {
      XOR_dic (in) i chaine cvs append cvlit
         [ logicWireLength neg inter i .5 add mul ] cvx put
      /i i 1 add store
   } repeat
   /i 0 def
   logicNInput {
      [logicUnit inter i .5 add mul dupp logicWireLength neg logicUnit sub 0 addv] ligne
      /i i 1 add store
   } repeat
   gsave
   newpath
      z1 smoveto
      [z1 .. z6 .. z2] draw_
      [z2 z8] ligne_
      [z8 .. z9 .. z7] draw_
      [z7 z1] ligne_
      blanc fill
   grestore
   [z1 .. z6 .. z2] draw
   [z2 z3] ligne
   [z3 {right} .. {1 -2} z4] draw
   [z4 {-1 -2} .. {left} z5] draw
   [z5 z1] ligne
   [z8 .. z9 .. z7] draw
   /logicNInput 2 store
end
grestore
} def

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

/NXOR_dic 15 dict def
/NXOR_dim {
   logicWireLength neg 0 jtoppoint
   5.85 logicUnit mul logicWireLength add 4 logicUnit mul jtoppoint
} def
/NXOR {
gsave
8 dict begin
   currentpoint translate
   /h_nxor 4 logicUnit mul def
   /inter h_nxor logicNInput div def
   .75  0 logicUnit mulv /z1 defpoint
   .75  4 logicUnit mulv /z2 defpoint
   2.25 4 logicUnit mulv /z3 defpoint
   5.25 2 logicUnit mulv /z4 defpoint
   2.25 0 logicUnit mulv /z5 defpoint
   1.5  2 logicUnit mulv /z6 defpoint
   0    0 logicUnit mulv /z7 defpoint
   0    4 logicUnit mulv /z8 defpoint
   .75  2 logicUnit mulv /z9 defpoint
   z4 .3 logicUnit mul 0 addv .3 logicUnit mul cercle
   [z4 .6 logicUnit mul 0 addv dupp logicWireLength 0 addv] ligne
   /i 0 def
   NXOR_dic /out {5.85 2 logicUnit mulv logicWireLength 0 addv} bind put
   logicNInput {
      NXOR_dic (in) i chaine cvs append cvlit
         [ logicWireLength neg inter i .5 add mul ] cvx put
      /i i 1 add store
   } repeat
   /i 0 def
   logicNInput {
      [logicUnit inter i .5 add mul dupp logicWireLength neg logicUnit sub 0 addv] ligne
      /i i 1 add store
   } repeat
   gsave
   newpath
      z1 smoveto
      [z1 .. z6 .. z2] draw_
      [z2 z8] ligne_
      [z8 .. z9 .. z7] draw_
      [z7 z1] ligne_
      blanc fill
   grestore
   [z1 .. z6 .. z2] draw
   [z2 z3] ligne
   [z3 {right} .. {1 -2} z4] draw
   [z4 {-1 -2} .. {left} z5] draw
   [z5 z1] ligne
   [z8 .. z9 .. z7] draw
   /logicNInput 2 store
end
grestore
} def

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

/INV_dic 15 dict def
/INV_dim {
   logicWireLength neg 0 jtoppoint
   3.198 logicUnit mul logicWireLength add 3 logicUnit mul jtoppoint
} def
/INV {
gsave
8 dict begin
   currentpoint translate
   /h_inv 3 logicUnit mul def
   /inter h_inv logicNInput div def
   0      0  logicUnit mulv /z1 defpoint
   0     3   logicUnit mulv /z2 defpoint
   2.598 1.5 logicUnit mulv /z3 defpoint
   3.198 1.5 logicUnit mulv /z4 defpoint
   z3 .3 logicUnit mul 0 addv .3 logicUnit mul cercle   
   [z1 z2 z3] polygone
   [z3 .6 logicUnit mul 0 addv dupp logicWireLength 0 addv] ligne
   INV_dic /out {3.198 1.5 logicUnit mulv logicWireLength 0 addv} bind put
   INV_dic /in {logicWireLength neg 1.5 logicUnit mul} bind put
   [logicWireLength neg 1.5 logicUnit mul 0 1.5 logicUnit mul] ligne
end
grestore
} def

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

/BUF_dic 15 dict def
/BUF_dim {
   logicWireLength neg 0 jtoppoint
   2.598 logicWireLength 2 mul add 3 logicUnit mulv jtoppoint
} def
/BUF {
gsave
8 dict begin
   currentpoint translate
   /h_buf 3 logicUnit mul def
   /inter h_buf logicNInput div def
   0   0     logicUnit mulv /z1 defpoint
   0   3     logicUnit mulv /z2 defpoint
   2.598 1.5 logicUnit mulv /z3 defpoint
   3.198 1.5 logicUnit mulv /z4 defpoint
   [z1 z2 z3] polygone
   [z3 dupp logicWireLength 0 addv] ligne
   /i 0 def
   BUF_dic /out {2.598 1.5 logicUnit mulv logicWireLength 0 addv} bind put
   BUF_dic /in {logicWireLength neg 1.5 logicUnit mul} bind put
   [logicWireLength neg 1.5 logicUnit mul 0 1.5 logicUnit mul] ligne
end
grestore
} def

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%ù

/skipnode {
   /loadnodedict    false def
   /n@deencours     false def
   /dian@deencours  false def
   /ovaln@deencours false def 
   /cn@deencours    false def
   /Cn@deencours    false def
} def

/ADD_dic 15 dict def
/ADD_dim {
   logicWireLength neg 0 jtoppoint
   5 logicUnit mul logicWireLength add 4 logicUnit mul jtoppoint
} def
/ADD {
gsave
8 dict begin
   currentpoint translate
   0 0 logicUnit mulv /z1 defpoint
   5 0 logicUnit mulv /z2 defpoint
   5 4 logicUnit mulv /z3 defpoint
   0 4 logicUnit mulv /z4 defpoint
   /in0 {0 1 logicUnit mulv logicWireLength neg 0 addv} def
   /in1 {0 2 logicUnit mulv logicWireLength neg 0 addv} def
   /in2 {0 3 logicUnit mulv logicWireLength neg 0 addv} def
   /out0 {5 1 logicUnit mulv logicWireLength 0 addv} def
   /out1 {5 3 logicUnit mulv logicWireLength 0 addv} def
   [in0 in1 in2] {dupp exch pop 0 exch (-) line} papply
   [out0 out1] {dupp exch pop 5 logicWireLength mul exch (-) line} papply
   [z1 z2 z3 z4] polygone
   10 dict begin
      skipnode
      12 setfontsize
      setTimes
   %  (\275 ADD) z1 z3 milieu cctext
     (ADD) z1 z3 milieu cctext
   end

   ADD_dic /remin {0 1 logicUnit mulv logicWireLength neg 0 addv} bind put
   ADD_dic /in0 {0 1 logicUnit mulv logicWireLength neg 0 addv} bind put
   ADD_dic /in1 {0 2 logicUnit mulv logicWireLength neg 0 addv} bind put
   ADD_dic /in2 {0 3 logicUnit mulv logicWireLength neg 0 addv} bind put
   ADD_dic /out0 {5 1 logicUnit mulv logicWireLength 0 addv}  bind put
   ADD_dic /out1 {5 3 logicUnit mulv logicWireLength 0 addv}  bind put
   ADD_dic /sum {5 1 logicUnit mulv logicWireLength 0 addv}  bind put
   ADD_dic /rem {5 3 logicUnit mulv logicWireLength 0 addv}  bind put
end
grestore
} def

/DemiADD_dic 21 dict def
/DemiADD_dim {
   logicWireLength neg 0 jtoppoint
   5 logicUnit mul logicWireLength add 4 logicUnit mul jtoppoint
} def
/DemiADD {
gsave
8 dict begin
   currentpoint translate
   0 0 logicUnit mulv /z1 defpoint
   5 0 logicUnit mulv /z2 defpoint
   5 4 logicUnit mulv /z3 defpoint
   0 4 logicUnit mulv /z4 defpoint
   /in0 {0 1 logicUnit mulv logicWireLength neg 0 addv} def
   /in1 {0 3 logicUnit mulv logicWireLength neg 0 addv} def
   /out0 {5 1 logicUnit mulv logicWireLength 0 addv} def
   /out1 {5 3 logicUnit mulv logicWireLength 0 addv} def
   [in0 in1] {dupp exch pop 0 exch (-) line} papply
   [out0 out1] {dupp exch pop 5 logicWireLength mul exch (-) line} papply
   [z1 z2 z3 z4] polygone
   10 dict begin
      skipnode
      12 setfontsize
      setTimes
     (\275 ADD) z1 z3 milieu cctext
   end

   DemiADD_dic /in0 {0 1 logicUnit mulv logicWireLength neg 0 addv}  bind put
   DemiADD_dic /in1 {0 3 logicUnit mulv logicWireLength neg 0 addv}  bind put
   DemiADD_dic /out0 {5 1 logicUnit mulv logicWireLength 0 addv}  bind put
   DemiADD_dic /out1 {5 3 logicUnit mulv logicWireLength 0 addv}  bind put
   DemiADD_dic /sum {5 1 logicUnit mulv logicWireLength 0 addv}  bind put
   DemiADD_dic /rem {5 3 logicUnit mulv logicWireLength 0 addv}  bind put
end
grestore
} def

%% /SQUARESYMBOL_dic 25 dict def
%% /SQUARESYMBOL_dim {
%%    0 0 jtoppoint
%%    4 logicUnit mul dup jtoppoint
%% } def
%% /SQUARESYMBOL {
%% gsave
%% 8 dict begin
%%    currentpoint translate
%%    /taille_fonte exch def
%%    /le_nom exch def
%%    0 0 logicUnit mulv /z1 defpoint
%%    4 0 logicUnit mulv /z2 defpoint
%%    4 4 logicUnit mulv /z3 defpoint
%%    0 4 logicUnit mulv /z4 defpoint
%%    [z1 z2 z3 z4] polygone
%%    /in0 {0 1 logicUnit mulv logicWireLength neg 0 addv} def
%%    /in1 {0 2 logicUnit mulv logicWireLength neg 0 addv} def
%%    /in2 {0 3 logicUnit mulv logicWireLength neg 0 addv} def
%%    /out0 {4 1 logicUnit mulv logicWireLength 0 addv} def
%%    /out1 {4 2 logicUnit mulv logicWireLength 0 addv} def
%%    /out1 {4 3 logicUnit mulv logicWireLength 0 addv} def
%%    10 dict begin
%%       skipnode
%%       taille_fonte setfontsize
%%       setTimes
%%       le_nom z1 z3 milieu cctext
%%    end
%% 
%%    SQUARESYMBOL_dic /in0 {0 1 logicUnit mulv} bind put
%%    SQUARESYMBOL_dic /in1 {0 2 logicUnit mulv} bind put
%%    SQUARESYMBOL_dic /in2 {0 3 logicUnit mulv} bind put
%%    SQUARESYMBOL_dic /out0 {4 1 logicUnit mulv}  bind put
%%    SQUARESYMBOL_dic /out1 {4 2 logicUnit mulv}  bind put
%%    SQUARESYMBOL_dic /out2 {4 3 logicUnit mulv}  bind put
%%    SQUARESYMBOL_dic /up0 {1 4 logicUnit mulv}  bind put
%%    SQUARESYMBOL_dic /up1 {2 4 logicUnit mulv}  bind put
%%    SQUARESYMBOL_dic /up2 {3 4 logicUnit mulv}  bind put
%%    SQUARESYMBOL_dic /down0 {1 0      logicUnit mulv}  bind put
%%    SQUARESYMBOL_dic /down1 {2 0      logicUnit mulv}  bind put
%%    SQUARESYMBOL_dic /down2 {3 0      logicUnit mulv}  bind put
%% end
%% grestore
%% } def

/DemiADDmod_dic 21 dict def
/DemiADDmod_dim {
   logicWireLength neg dup jtoppoint
   4 logicUnit mul logicWireLength add 4 logicUnit mul jtoppoint
} def
/DemiADDmod {
gsave
8 dict begin
   currentpoint translate
   0 0 logicUnit mulv /z1 defpoint
   4 0 logicUnit mulv /z2 defpoint
   4 4 logicUnit mulv /z3 defpoint
   0 4 logicUnit mulv /z4 defpoint
   /in0 {0 1 logicUnit mulv logicWireLength neg 0 addv} def
   /in1 {0 3 logicUnit mulv logicWireLength neg 0 addv} def
   /out0 {4 2 logicUnit mulv logicWireLength 0 addv} def
   /out1 {2 0 logicUnit mulv 0 logicWireLength neg addv} def
   [in0 in1] {dupp exch pop 0 exch (-) line} papply
   out0 dupp exch pop 4 logicWireLength mul exch (-) line
   out1 dupp pop 0 (-) line
   [z1 z2 z3 z4] polygone
   10 dict begin
      skipnode
      12 setfontsize
      setTimes
     (\275 Add) z1 z3 milieu cctext
   end

   DemiADDmod_dic /in0 {0 1 logicUnit mulv logicWireLength neg 0 addv}  bind put
   DemiADDmod_dic /in1 {0 3 logicUnit mulv logicWireLength neg 0 addv}  bind put
   DemiADDmod_dic /out0 {4 2 logicUnit mulv logicWireLength 0 addv}  bind put
   DemiADDmod_dic /out1 {2 0 logicUnit mulv 0 logicWireLength neg addv} bind put
   DemiADDmod_dic /rem {2 0 logicUnit mulv 0 logicWireLength neg addv} bind put
   DemiADDmod_dic /sum {4 2 logicUnit mulv logicWireLength 0 addv}  bind put
end
grestore
} def

/ADDmod_dic 15 dict def
/ADDmod_dim {
   logicWireLength neg dup jtoppoint
   5 logicUnit mul logicWireLength add 4 logicUnit mul logicWireLength add jtoppoint
} def
/ADDmod {
gsave
8 dict begin
   currentpoint translate
   0 0 logicUnit mulv /z1 defpoint
   5 0 logicUnit mulv /z2 defpoint
   5 4 logicUnit mulv /z3 defpoint
   0 4 logicUnit mulv /z4 defpoint
   /in0 {1 4 logicUnit mulv 0 logicWireLength addv} def
   /in1 {0 1 logicUnit mulv logicWireLength neg 0 addv} def
   /in2 {0 3 logicUnit mulv logicWireLength neg 0 addv} def
   /out0 {5 2 logicUnit mulv logicWireLength 0 addv} def
   /out1 {2.5 0 logicUnit mulv 0 logicWireLength neg addv} def
   in0 dupp pop 4 logicUnit mul (-) line
   out1 dupp pop 0 (-) line
   [in1 in2] {dupp exch pop 0 exch (-) line} papply
   out0 dupp exch logicWireLength sub exch (-) line
   [z1 z2 z3 z4] polygone
   10 dict begin
      skipnode
      20 setfontsize
      setTimes
     (+) z1 z3 milieu cctext
   end

   ADDmod_dic /in0 {1 4 logicUnit mulv 0 logicWireLength addv}  bind put
   ADDmod_dic /remin {1 4 logicUnit mulv 0 logicWireLength addv}  bind put
   ADDmod_dic /in2 {0 1 logicUnit mulv logicWireLength neg 0 addv} bind put
   ADDmod_dic /in1 {0 3 logicUnit mulv logicWireLength neg 0 addv} bind put
   ADDmod_dic /out0 {5 2 logicUnit mulv logicWireLength 0 addv}  bind put
   ADDmod_dic /sum {5 2 logicUnit mulv logicWireLength 0 addv}  bind put
   ADDmod_dic /out1 {2.5 0 logicUnit mulv 0 logicWireLength neg addv} bind put
   ADDmod_dic /rem {2.5 0 logicUnit mulv 0 logicWireLength neg addv} bind put
end
grestore
} def

/GATE_dic 35 dict def
/GATE_dim {
5 dict begin
   3 copy
   pop pop
   /n exch def
   /nd n 1000 div floor cvi def
   /n n nd 1000 mul sub store
   /nl n 100 div floor cvi def
   /n n nl 100 mul sub store
   /nu n 10 div floor cvi def
   /n n nu 10 mul sub store
   /nr n cvi def
   nl 0 ne {/nl 1 store} if
   nu 0 ne {/nu 1 store} if
   nr 0 ne {/nr 1 store} if
   nd 0 ne {/nd 1 store} if
   logicWireLength neg nl mul
   logicWireLength neg nd mul
   jtoppoint
   4 logicUnit mul logicWireLength nr mul add
   4 logicUnit mul logicWireLength nu mul add
   jtoppoint
end
} def

/GATE {
gsave
8 dict begin
   currentpoint translate
   /n exch def
   /taille_fonte exch def
   /le_nom exch def
   0 0 logicUnit mulv /z1 defpoint
   4 0 logicUnit mulv /z2 defpoint
   4 4 logicUnit mulv /z3 defpoint
   0 4 logicUnit mulv /z4 defpoint
   [z1 z2 z3 z4] polygone

   /nd n 1000 div floor cvi def
   /n n nd 1000 mul sub store
   /nl n 100 div floor cvi def
   /n n nl 100 mul sub store
   /nu n 10 div floor cvi def
   /n n nu 10 mul sub store
   /nr n cvi def

   /h_and 4 logicUnit mul def
   nl 0 ne {
      /inter h_and nl div def
      /i 0 def
      nl {
         GATE_dic (l) i chaine cvs append cvlit
            [ logicWireLength neg inter i .5 add mul ] cvx put
         [ 0 inter i .5 add mul dupp logicWireLength neg 0 addv] ligne
         /i i 1 add store
      } repeat
   } if

   nr 0 ne {
      /inter h_and nr div def
      /i 0 def
      nr {
         GATE_dic (r) i chaine cvs append cvlit
            [ logicWireLength 4 logicUnit mul add inter i .5 add mul ] cvx put
         [ 4 logicUnit mul inter i .5 add mul dupp logicWireLength 0 addv] ligne
         /i i 1 add store
      } repeat
   } if

   nu 0 ne {
      /inter h_and nu div def
      /i 0 def
      nu {
         GATE_dic (u) i chaine cvs append cvlit
            [ inter i .5 add mul 4 logicUnit mul logicWireLength add ] cvx put
         [ inter i .5 add mul 4 logicUnit mul dupp 0 logicWireLength addv] ligne
         /i i 1 add store
      } repeat
   } if

   nd 0 ne {
      /inter h_and nd div def
      /i 0 def
      nd {
         GATE_dic (d) i chaine cvs append cvlit
            [ inter i .5 add mul 0 logicWireLength sub ] cvx put
         [ inter i .5 add mul 0 dupp 0 logicWireLength subv] ligne
         /i i 1 add store
      } repeat
   } if

   10 dict begin
      skipnode
      taille_fonte setfontsize
      setTimes
      le_nom z1 z3 milieu cctext
   end

end
grestore
} def